Multi-port memory devices, including dual-port devices, can be preferred over single-port memory devices, as data values can be read and written simultaneously.
To better understand various aspects and advantages of the disclosed embodiments, two conventional dual-port type memory cells will now be described.
A first conventional dual-port type memory cell is set forth in FIG. 8, and designated by the general reference character 800. The example of FIG. 8 shows a “true” eight transistor (8-T) dual-port cell. The memory cell 800 includes cross-coupled inverters INV1 and INV2, each of which can be a complementary-metal-oxide-semiconductor (CMOS) inverter, and thus include two transistors. Inverters (INV1 and INV2) can form a latch, or flip—flip, that stores a data value on complementary data nodes (D and DB). A dual-port capability is provided by access transistors M1 to M4. Transistors M1 and M2 can be commonly enabled by a first word line WL1 to read or write data for a first port by way of complementary bit lines BL1 and BLB1. Similarly, transistors M3 and M4 can be commonly enabled by a second word line WL2 to read or write data for a second port by way of complementary bit lines BL2 and BLB2.
A drawback to the conventional arrangement of FIG. 8 can be the resulting signal routing needed. In particular, such an arrangement typically requires two pairs (four total) of metal routes for the bit line pairs (BL1/BLB1 and BL2/BLB2). This can lead to undesirable crowding at such a metal layer.
A second conventional dual-port type memory cell is set forth in FIG. 9, and designated by the general reference character 900. The example of FIG. 9 shows a “quasi” dual-port cell that can be implemented with six transistors. Like the 8-T cell of FIG. 8, memory cell 900 also includes cross-coupled inverters INV1 and INV2. A quasi dual-port capability is provided by access transistors M8 and M9. Transistor M8 is activated by a first word line WL1, to read or write data for a first port by way of bit line BL1. Transistor M9 is activated by a second word line WL2 to read or write data for a second port by way of bit line BLB2.
While the conventional arrangement of FIG. 9 can provide a more compact cell (i.e., six transistors instead of eight), such an arrangement can have drawbacks.
A drawback to the arrangement of FIG. 9 can be specialized circuitry, multiple operating voltages, additional process steps and/or decreased reliability that may be needed to properly write data into the cell. In particular, because a write operation only provides data via a single bit line (BL1 or BLB2), a write operation must be capable of forcing a latch (INV1/INV2) into a data state from only one data node (D or DB). In order to ensure that a write voltage is sufficiently high, a boosted gate voltage can be applied to the access transistor (M8 or M9). Thus, the circuit of FIG. 9 can require “boosted” (higher than supply) gate voltages and/or a dynamic power supply. Such higher operating voltages can require extra process steps, such as increased gate oxide thickness, as but one example. If increased gate oxide thickness is not employed, such higher operating voltages can stress gate oxide layers, decreasing reliability.
Another drawback to the arrangement of FIG. 9 can be slower performance. The memory cell 900 of FIG. 9 is not a “true” dual-port cell in that accesses to the cell are typically multiplexed.
In light of the above, it would be desirable to arrive at some sort of multi-port memory cell that has a more compact structure than a conventional 8-T dual-port cell, but does not suffer from the various drawbacks of a 6-T quasi dual-port cell.